1. Field of the Invention
The present invention relates generally to programmable logic arrays, and more particularly, a programmable logic array which outputs a logic signal previously programmed in synchronization with an external clock signal.
2. Description of the Prior Art
With the progress of ASIC (application specific IC) of a logic VLSI (very-large-scale integrated circuit), it is important to make use of a logic macro-cell in order to design the logic VLSI having a high performance and high density for a short time period. Therefore, it is considered that a programmable logic array is effective as an element for treating irregular logic as a macro-unit.
Since the programmable logic array has simple logical structure, i.e., two-stage logical structure comprising an OR (logical sum) circuit and an AND (logical product) circuit, the programmable logic array has the advantages that the logic design is easily made, the logic design can be automated, and the change of design is easily made by only changing a single mask. In addition, since the programmable logic array has structure suitable for an integrated circuit, integration density is easily increased. Furthermore, since the programmable logic array has regular structure, failures are easily tested.
FIG. 1 is an electric circuit diagram showing one example of a conventional programmable logic array.
Referring now to FIG. 1, description is made on the structure of the conventional programmable logic array. The programmable logic array includes an OR circuit 67 and an AND circuit 68. The OR circuit 67 comprises input signal lines 51 to 53 receiving signals applied to input terminals 2, 3 and 4, respectively, and inverted input signal lines 48 to 50 receiving signals obtained by inverting the signals by inverters 7 to 9, respectively. Product term lines 57 to 60 and ground lines 61 and 62 are provided perpendicularly intersecting with the input signal lines 51 to 53 and the inverted input signal lines 48 to 50. The ground lines 61 and 62 have their respective one ends connected to ground through n channel transistors 35 and 36, respectively. In addition, the product term lines 57 to 60 have their respective one ends connected to supply terminals 71 to 74 through p channel transistors 31 to 34, respectively. The n channel transistors 35 and 36 and the p channel transistors 31 to 34 have their gates connected to a clock input terminal 1 by a clock signal line 47. In addition, n channel transistors 66, 78 and 79 are connected to intersections of the inverted input signal lines 48 to 50 and the product term lines 57 to 60 and the ground lines 61 and 62 as required, to be programmed.
On the other hand, an output of the OR circuit 67 is transmitted to the AND circuit 68 through inverters 20 to 27 from the product term lines 57 to 60. Output lines 54 and 55 and a ground line 56 are provided perpendicularly intersecting with the product term lines 57 to 60. The ground line 56 has its one end connected to ground through an n channel transistor 41. In addition, the output lines 54 and 55 have their respective one ends connected to supply terminals 76 and 77 through p channel transistors 39 and 40, respectively. The output lines 54 and 55 have their respective other ends connected to latch circuits respectively comprising inverters 11 and 12 and 14 and 15 through inverters 16 to 19 and n channel transistors 43 and 45, and connected to output terminals 5 and 6 through inverters 10 and 13, respectively.
The n channel transistors 43 and 44 have their gates connected to a clock input terminal 1. In addition, the p channel transistors 39 and 40 and the n channel transistor 41 are opened or closed in response to a clock signal applied through a p channel transistor 37 and inverters 28 to 30. The p channel transistors 39 and 40 have their drains connected to the supply terminals 76 and 77, respectively. Furthermore, n channel transistors 80 and 81 are connected to respective intersections of the product term lines 57 to 60 and the output lines 54 and 55 and the ground line 56 in the AND circuit 68 as required, to be programmed.
Description is now made on an operation of the conventional programmable logic array shown in FIG. 1. Signals inputted from the input signal terminals 2 to 4 are transmitted to the input signal lines 51 to 53, respectively. In addition, the signals are inverted by the inverters 7 to 9, to be transmitted to the inverted signal input lines 48 to 50, respectively. When the clock signal is inputted to the clock input terminal 1 and the clock signal is at an "L" level, a clock gate comprising the p channel transistors 31 to 34 is opened. Consequently, voltages are applied to the product term lines 57 to 60 from the supply terminals 71 to 74, respectively, so that the product term lines 57 to 60 are precharged, to attain an "H" level.
Then, when the clock signal attains the "H" level, a clock gate comprising the n channel transistors 35 and 36 is opened. Consequently, only a transistor having its gate connected to the input signal line at the "H" level is rendered conductive, so that charges stored in any of the product term lines 57 to 60 are discharged, whereby any of the product term lines whose charges are discharged attains the "L" level. At that time, the n channel transistor 41 is also opened. Thus, in the AND circuit 8, charges are stored and discharged in the output signal lines 54 and 55, so that suitable output logic can be obtained.
However, in the conventional programmable logic array shown in FIG. 1, a power-supply voltage V.sub.DD is directly applied to the product term lines 57 to 60 and the output lines 54 and 55, so that a long time is required for discharging after the product term lines 57 to 60 and the output lines 54 and 55 are charged. This is one factor which prevents speeding up of the operation.